1. Technical Field
Various embodiments generally relate to a semiconductor integrated circuit device, more particularly, to a vertical transistor and a variable resistive memory device including the vertical transistor.
2. Related Art
A semiconductor integrated circuit device may be highly integrated. Thus, in order to form a plurality of memory cells in a small area of the semiconductor integrated circuit device, a vertical transistor may be developed.
The vertical transistor may include a channel vertically formed on a semiconductor substrate. The vertical transistor may include a pillar-shaped active region.
The vertical transistor may include a gate, a source, and a drain. The gate may be configured to surround the pillar. The source may be formed in, under, or over the pillar and at one side of the gate. The drain may be formed in the pillar and at the other side of the gate. Further, the channel of the vertical transistor may be formed in the pillar and between the source and the drain.
Unlike a channel of a planar MOS transistor, the channel of the pillar-shaped vertical transistor may float. Therefore, a leakage current may occur due to the floating channel.
Particularly, when a voltage may be applied to the gate and the drain, a high electric field may be concentrated on an edge of the gate, particularly a boundary between the gate and the drain so that a gate induced drain leakage (GIDL) may be generated. The GIDL may become more serious in the floating channel.